1. Field of the Invention
The present invention relates to an analysis method for a semiconductor device in a manufacturing process thereof, an analysis system, and a computer program product.
2. Description of the Related Art
Along with advances in multifunction semiconductor devices such as a semiconductor integrated circuit, reduction of pattern dimensions and large-scale integration are in constant demand. It is necessary to manufacture such a semiconductor device in a plurality of chip regions on a semiconductor substrate with a uniform performance and a high manufacturing yield. In a manufacturing method for the semiconductor device, various manufacturing processes are used. In order to improve the manufacturing yield of the semiconductor device, it is necessary to improve a yield rate for each of the manufacturing processes. Hence, failure analysis occurring in the semiconductor device due to the manufacturing processes is important.
For the purpose of achieving an optimum condition for a manufacturing process of the semiconductor device, developing a new process, controlling a process, or the like, the manufacturing process is often evaluated using a test pattern formed on a semiconductor substrate. Usually, the failure analysis of test element group (TEG) data is implemented by use of various types of TEGs fabricated on a chip or a wafer for evaluating the manufacturing processes. Failures that occur in a manufacturing process are classified into a systematic failure due to the manufacturing process and a random failure which accidently occurs. In the TEG failure analysis, the systematic failure is classified from among the failures occurring in the TEG in order to extract problems in the manufacturing process associated with the systematic failure. A method is known for controlling the quality of a semiconductor device where non-defective chips in the semiconductor substrate are extracted and a relationship between a yield rate for electrical characteristics of TEGs in the non-defective chips and parameters of the manufacturing process is analyzed to identify the cause of deterioration of a manufacturing yield by the systematic failure (refer to Japanese Patent Laid-Open Application No. 2001-110867).
In development of a manufacturing process of a semiconductor device, currently, failures in each particular TEG fabricated on a chip or a wafer are analyzed by empirical methods to estimate the reason for a systematic failure. However, it is difficult to identify a parameter closely related to the failures by a method based on failure analysis of each particular TEG. Thus, there is a possibility that an underlying problem of the manufacturing process may not be detected and, thereby, be unidentified.